The present invention relates to an interposer and a method for manufacturing an interposer, more specifically an interposer including a dielectric thin film of very high dielectric constant, and a method for manufacturing the interposer.
Recently, the digital LSIs (Large Scale Integrated circuits), etc., typically microprocessors have the operation speed increased and the electric power consumption lowered.
In order to operate the LSI in the high-frequency range of the GHz band and at low voltage, it is very important to suppress the power source voltage fluctuation due to abrupt fluctuations of the load impedance, etc. of the LSI while removing high-frequency noises of the power source.
Conventionally, the power source voltage has been regulated, and the high-frequency noises have been removed, by mounting decoupling capacitors near the LSI, etc. mounted on a printed circuit board. The decoupling capacitors are formed on a substrate different from the printed circuit board and are suitably mounted on the printed circuit board.
However, in mounting the decoupling capacitors near the LSI mounted on the printed circuit board, the LSI and the decoupling capacitors are electrically connected to each other via the interconnections formed on the printed circuit board, whereby large inductance due to the wiring of the interconnections is present. With the large inductance present between the LSI and the decoupling capacitors, the power source voltage cannot be sufficiently regulated, and the high-frequency noises cannot be sufficiently removed. For the sufficient regulation of the source voltage and the high-frequency noise removal, it is required to decrease the equivalent serial resistance (ESR) and the equivalent serial inductance (ESL).
Here, the technique of disposing interposers with capacitors built in are disposed between the LSI and the printed circuit board is noted (Patent References 1 to 6).
Following references disclose the background art of the present invention.
[Patent Reference 1]
Specification of Japanese Patent Application Unexamined Publication No. Hei 4-211191
[Patent Reference 2]
Specification of Japanese Patent Application Unexamined Publication No. Hei 7-176453
[Patent Reference 3]
Specification of Japanese Patent Application Unexamined Publication No. 2001-68583
[Patent Reference 4]
Specification of Japanese Patent Application Unexamined Publication No. 2001-35990
[Patent Reference 5]
Specification of Japanese Patent Application Unexamined Publication No. 2004-304159
[Patent Reference 6]
Specification of Japanese Patent Application Unexamined Publication No. 2002-83892
[Patent Reference 7]
Specification of Japanese Patent Application Unexamined Publication No. 2006-60119
[Non-Patent Reference 1]
K. Matsumaru et al., “Transmission characteristics of the Silicon Through-hole Interconnections and the Glass Through-hole Interconnections”, The 15th Microelectronics Symposium (MES2005), October, 2005, p. 193-196
However, in the technique disclosed in Patent References 1-5, through-holes must be formed in a semiconductor substrate, etc. so as to bury through-electrodes in the semiconductor substrate, etc. It takes long time and high cost to form the through-holes in the semiconductor substrate, etc. Accordingly, it is very difficult to decrease the cost by the technique disclosed in Patent references 1-5.
In the technique disclosed in Patent Reference 6, films are formed on an organic film (resin layer) to form capacitors, which makes it impossible to form the dielectric film of good crystallinity, because when a dielectric film is formed on a resin layer, whose heat resistance is not so high, the process for forming the dielectric film is limited to 400° C. or below. The dielectric film formed on a resin layer generally has a dielectric constant of about 20, and the high dielectric constant is about 50 at highest. Thus, the capacitors of high dielectric constant cannot be realized.